Integral INSSD64GP25MXZ Scheda Tecnica Scaricare il pdf (Pagina 5)

5

31

INTRQ

32

IOIS16

33

DA1

34

-PDIAG:-CBLID

35

DA0

36

DA2

37

-CS0

38

-CS1

39

-DASP

40

GND

41

VCC

42

VCC

43

GND

44

NC

2.2 Pin Description

Pin No.

Signal

I/O*

Description

01

-RESET

I

Hardware reset signal from the

host

17,15,13,11,09,07,

05,03,04,06,08,10,

12,14,16,18

DD0~DD15(Device

Data)

I/O

16-bit bi-direction Data Bus.

DD(7:0) are used for 8-bit

register transfers.

21

DMARQ(DMA Request)

O

For DMA data transfers.

Device will assert DMARQ

when the device is ready to

transfer data to or from the

host.

-DIOW(I/O Write)

This is the strobe signal used

by the host to write to the

device register or Data port

23

STOP(Stop UDMA

Burst)

I

The host assert this signal

during an UDMA burst to stop

the DMA burst

1 2 3 4 5 6 7 8 9 10 ... 24 25

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